Oliver Diessel

Associate Professor

Dr Oliver Diessel is an Associate Professor in the School of Computer Science and Engineering.

Research interests

 

I develop methods for the design, test and implementation of digital systems in reconfigurable logic devices called Field-Programmable Gate Arrays.

My interest is in dynamically reconfigurable digital systems in which the circuits are modified while the system is operational.

I aim to promote the use of reconfigurable systems through the development of architectures, design methods and tools that enhance their benefits and reduce their costs.

Interest in engineering

Why did you get into engineering?

A fascination with technology and a natural tendency towards mathematics and science.

What are your research goals?

To develop smart devices that can act independently to benefit people.

What do people not understand about what you do?

They think I can help with practical issues such as fixing their PC or advising them on the best machine to buy. They would be better off asking me some theoretical questions.

Advice for prospective computer engineers & scientists

A career in computer engineering or computer science can see you changing the world. With this great power comes great responsibility. Keep an open mind to the wider implications of what you learn and do. And follow your dream.

Lectures/Courses taught

Configurable Systems

COMP4601 – Design Project B, UNSW (2009 – present)

Computer Architecture

COMP4211 – Advanced Architectures and Algorithms, UNSW (2004 – 2006)

COMP3211 – Computer Architecture, UNSW (2002 – 2006, 2012)

Digital Systems

COMP3222 – Digital Circuits and Systems, UNSW (2008, 2010 – present)

FPGA Implementation of Digital Systems using Verilog, Harbin Institute of Technology (2014 - present)

COMP2021 – Digital Systems Structures, UNSW (2000 – 2004)

FPGA Design Course, Ho Chi Minh City University of Technology (2003)

Computer Programming

COMP1921 – Data Structures and Algorithms, UNSW (2008 – 2009)

XCMP1000 – Computing 1, UNSW Asia (2007)

COMP1021 – Computing 1B, UNSW (2005)

Professional Issues & Ethics

COMP4920 – Professional Issues and Ethics, UNSW (2001)

Students

Number currently in lab: 2

Number graduated: 6

Student Projects:

Current students work on design of fault-tolerant FPGA-based systems for space and fine-grained accelerators for heterogeneous devices.

Previous students have worked on multi-core task migration, the verification of dynamically reconfigurable systems, communications infrastructure for module-based dynamically reconfigurable systems, and configuration encoding techniques for rapid reconfiguration.

Looking for students for projects related to:

Dynamic modular reconfiguration of FPGA-based TMR circuits. This project involves the development of techniques to meet reliability, performance and resource constraints for SRAM FPGA-based implementations of digital systems to recover from radiation-induced Single Event Upsets. We are investigating design approaches, CAD tools for circuit synthesis, partitioning and layout, and benchmarking with circuits typical of applications deployed in space.

Run-time validation of FPGA-based computations. Computational tasks hosted on FPGA devices are increasingly susceptible to run-time errors due to process variation, device degradation and radiation. This project seeks to develop efficient (better than TMR) techniques for checking the correctness of tasks while they are running. Another thrust is to validate dynamically acquired FPGA configurations.

Professional Organisations and Consulting positions

IEEE Member

Editorial Board, ACM Transactions on Reconfigurable Technology and Systems

Education

PhD/postgraduate

PhD, University of Newcastle, Australia, 1998

Undergraduate

B.E. (Computer, Hons), University of Newcastle, Australia, 1991

B.Math., University of Newcastle, Australia, 1991

publications

Conference Papers
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Tran Huu Nguyen N; Cetin E; Diessel O, 2019, 'Scheduling configuration memory error checks to improve the reliability of FPGA-based systems', in IET Computers and Digital Techniques, pp. 198 - 205, http://dx.doi.org/10.1049/iet-cdt.2018.5001
2019
Kastensmidt FL; Diessel O, 2019, '2019 Reconfigurable Architectures Workshop', in Proceedings - 2019 IEEE 33rd International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2019, pp. 69, http://dx.doi.org/10.1109/IPDPSW.2019.00018
2019
Kroh A; Diessel O, 2018, 'A Short-Transfer Model for Tightly-Coupled CPU-FPGA Platforms', in Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018, pp. 369 - 372, http://dx.doi.org/10.1109/FPT.2018.00075
2018
Agiakatsikas D; Lee G; Mitchell T; Cetin E; Diessel O, 2018, 'From C to Fault-Tolerant FPGA-Based Systems', in Proceedings - 26th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, pp. 212, http://dx.doi.org/10.1109/FCCM.2018.00046
2018
Nguyen NTH; Cetin E; Diessel O, 2017, 'Scheduling considerations for voter checking in TMR-MER systems', in Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, Napa, CA, USA, pp. 30 - 30, presented at 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, USA, 30 April 2017 - 02 May 2017, http://dx.doi.org/10.1109/FCCM.2017.17
2017
Nguyen NTH; Cetin E; Diessel O, 2017, 'Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems', in 2017 IEEE Int. Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, pp. 1 - 4, http://dx.doi.org/10.1109/DFT.2017.8244455
2017
Gong L; Kroh A; Agiakatsikas D; Nguyen NTH; Cetin E; Diessel O, 2017, 'Reliable SEU monitoring and recovery using a programmable configuration controller', in 2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017, Ghent, Belgium, presented at 2017 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium, 04 September 2017 - 08 September 2017, http://dx.doi.org/10.23919/FPL.2017.8056798
2017
Lee G; Agiakatsikas D; Wu T; Cetin E; Diessel O, 2017, 'TLegUp: A TMR code generation tool for SRAM-based FPGA applications using HLS', in Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, pp. 129 - 132, http://dx.doi.org/10.1109/FCCM.2017.57
2017
Zhao Z; Agiakatsikas D; Nguyen NT; Cetin E; Diessel O, 2016, 'Fine-grained Module-based Error Recovery in FPGA-based TMR Systems', in International Conference on Field-Programmable Technology (FPT), Xi'an, China, pp. 101 - 108, presented at International Conference on Field-Programmable Technology, Xi'an, China, 07 December 2016 - 09 December 2016, http://dx.doi.org/10.1109/FPT.2016.7929433
2016
Nguyen NTH; Cetin E; Diessel OF, 2016, 'Dynamic Scheduling of Voter Checks in FPGA-based TMR Systems', in The 2016 International Conference on Field-Programmable Technology (FPT'16), Xi'an, China, pp. M2 - M2, presented at The 2016 International Conference on Field-Programmable Technology (FPT'16), Xi'an, China, 07 December 2016 - 09 December 2016
2016
Agiakatsikas D; Cetin E; Diessel O, 2016, 'FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs', in Field Programmable Logic and Applications (FPL), 2016 26th International Conference on, EPFL, pp. 1 - 4, EPFL, http://dx.doi.org/10.1109/FPL.2016.7577339
2016
Nguyen NTH; Agiakatsikas D; Cetin E; Diessel O, 2016, 'Dynamic scheduling of voter checks in FPGA-based TMR systems', in Proceedings of the 2016 International Conference on Field-Programmable Technology, FPT 2016, Xi'an, China, pp. 169 - 172, presented at 2016 International Conference on Field-Programmable Technology (FPT), Xi'an, China, 07 December 2016 - 09 December 2016, http://dx.doi.org/10.1109/FPT.2016.7929525
2016
Agiakatsikas D; Nguyen NTH; Zhao Z; Wu T; Cetin E; Diessel O; Gong L, 2016, 'Reconfiguration Control Networks for TMR Systems with Module-based Recovery', in Proceedings - 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016, USA, pp. 88 - 91, presented at IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), USA, 01 May 2016 - 03 May 2016, http://dx.doi.org/10.1109/FCCM.2016.30
2016
Gong L; Wu T; Nguyen NTH; Agiakatsikas D; Zhao Z; Cetin E; Diessel OF, 2016, 'A Programmable Configuration Controller for Fault-Tolerant Applications', in The 2016 International Conference on Field-Programmable Technology (FPT'16), Xi'an, China, pp. 117 - 124, presented at The 2016 International Conference on Field-Programmable Technology (FPT'16), Xi'an, China, 07 December 2016 - 09 December 2016, http://dx.doi.org/10.1109/FPT.2016.7929515
2016
Tran VT; Shivaramaiah NC; Diessel O; Dempster AG, 2015, 'A programmable multi-gnss baseband receiver', in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, pp. 1178 - 1181, IEEE, http://dx.doi.org/10.1109/ISCAS.2015.7168849
2015
Leong PHW; Amano HC; Anderson J; Bertels K; Cardoso JMP; Diessel O; Gogniat G; Hutton M; Lee J; Luk W; others , 2015, 'Significant papers from the first 25 years of the FPL conference', in International Conference on Field Programmable Logic and Applications, IEEE, IEEE, http://dx.doi.org/10.1109/FPL.2015.7293747
2015
Cetin E; Diessel O; Gong L, 2015, 'Improving F max of FPGA circuits employing DPR to recover from configuration memory upsets', in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, pp. 1190 - 1193, IEEE, http://dx.doi.org/10.1109/ISCAS.2015.7168852
2015
Kroh A; Diessel O, 2015, 'Towards OS kernel acceleration in heterogeneous systems', in First International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC15), IEEE, IEEE
2015
Cetin E; Diessel O; Gong L; Lai V, 2014, 'Reconfiguration network design for SEU recovery in FPGAs', in Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1524 - 1527, http://dx.doi.org/10.1109/ISCAS.2014.6865437
2014
Diessel O, 2013, 'Opportunities and challenges for dynamic FPGA reconfiguration in electronic measurement and instrumentation', in Electronic Measurement & Instruments (ICEMI), 2013 IEEE 11th International Conference on, IEEE, pp. 258 - 263, IEEE, http://dx.doi.org/10.1109/ICEMI.2013.6743028
2013
Cetin E; Diessel O; Gong L; Lai V, 2013, 'Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration', in 2013 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto, Portugal, pp. 1 - 4, presented at 2013 23rd International Conference on Field Programmable Logic and Applications (FPL), Porto, Portugal, 02 September 2013 - 04 September 2013, http://dx.doi.org/10.1109/FPL.2013.6645571
2013
Lingkan G; Diessel OF, 2012, 'Functionally Verifying State Saving and Restoration in Dynamically Reconfigurable Systems', in ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, Association for Computing Machinery, New York, NY, United States, pp. 241 - 244, presented at 2012 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA'12, Monterey, California, USA, 22 February 2012 - 24 February 2012, http://dx.doi.org/10.1145/2145694.2145735
2012
Lingkan G; Diessel OF, 2011, 'ReSim: A Reusable Library for RTL Simulation of Dynamic Partial Reconfiguration', in International Conference on Field Programmable Technology, IEEE Computer Society, New York, NY, United States, pp. 1 - 8, presented at International Conference on Field-Programmable Technology, New Delhi, India, http://dx.doi.org/10.1109/FPT.2011.6132709
2011
Lingkan G; Diessel OF, 2011, 'Modeling Dynamically Reconfigurable Systems for Simulation-based Functional Verification', in IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, New York, NY, United States, pp. 9 - 16, presented at IEEE International Symposium on Field-Programmable Custom Computing Machines, Salt Lake City, Utah, USA, 01 May 2011 - 03 May 2011, http://dx.doi.org/10.1109/FCCM.2011.18
2011
Becker J; Benoit P; Cumplido R; Prasanna VK; Vaidyanathan R; Hartenstein R; Areibi S; Bampi S; Becker J; Benoit P; Bergmanr N; Brebner G; Buechner T; Cadenas O; Campi F; Carro L; Chen N; Cheung PYK; Cumplido R; Dandekar O; Diessel O; Jean-Philippe ; Diniz P; Donlin A; Elgindy H; Fahmy S; Glesner M; Gogniat G; Gu Y; Guccione S; Hariyama M; Hartenstein R; Heinkel U; Herkersdorf A; Hochberger C; Hollstein T; Jones A; Katkoori S; Koch A; Kress R; Krupnova H; Lagadec L; Lauwereins R; Leong P; Lysaght P; Marnane L; Mesquita D; Moraes F; Moreno M; Morra C; Morris J; Mukherjee A; Nakano K; Nunez-Yanez J; Ors B; Ou J; Pardo F; Parthasarathi R; Patterson C; Paulsson K; Pionteck T; Platzner M; Pottier B; Reis R; Santambrogio M; Sass R; Sassatelli G; Schaumont P; Schmeck H; Sezer S; Smit G; So H; Suttei G; Tanougast C; Teich J; Tessier R; Thomas D; Torres L; Trahan J; Torreser J; Vaidyanathan R; Valderrama C; Vanderbauwhede W; Vasilko M; Veale B; Vorbach M; Waldschmidt K; Wehn N, 2011, 'Raw introduction', pp. 125 - 127, http://dx.doi.org/10.1109/ipdps.2011.396
2011
Hredzak B; Diessel OF, 2011, 'Optimization of Placement of Dynamic Network-on-chip Cores Using Simulated Annealing', in IEEE, Proceedings of the 37th Annual Conference of the IEEE Industrial Electronics Society, Australia, pp. 2400 - 2405, presented at 37th Annual Conference of the IEEE Industrial Electronics Society, IECON 2011, Melbourne, VIC., Australia, 07 November 2011 - 10 November 2011, http://dx.doi.org/10.1109/IECON.2011.6119685
2011
Kwek B; Sunarso F; Teoh M; van Zaal A; Preston P; Diessel OF, 2010, 'FPGA-based video processing for a vision prosthesis', in Proceedings, 2010 International Conference on Field-Programmable Technology, IEEE, Beijing, China, pp. 345 - 348, presented at 2010 International Conference on Field-Programmable Technology, FPT 10, Beijing, China, 08 December 2010 - 10 December 2010, http://dx.doi.org/10.1109/FPT.2010.5681430
2010
Diessel O; Bergmann N; Shannon L, 2009, 'Message from the general chair and program co-chairs', in Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09, http://dx.doi.org/10.1109/FPT.2009.5377600
2009
Koh S; Diessel OF, 2008, 'The effectiveness of configuration merging in point-to-point networks', in IEEE symposium on field-programmable custom computing machines 2008, IEEE symposium on field-programmable custom computing machines 2008, Stanford, California, USA, presented at IEEE symposium on field-programmable custom computing machines 2008, Stanford, California, USA, 14 April 2008 - 15 April 2008
2008
Koh S; Diessel O, 2008, 'The effectiveness of configuration merging in point-to-point networks for module-based FPGA reconfiguration', in Proceedings of the 16th IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM'08, pp. 65 - 76, http://dx.doi.org/10.1109/FCCM.2008.25
2008
Kuo JY; Ku AK; Xue J; Diessel OF; Malik U, 2008, 'ACS: an addressless configuration support for efficient partial reconfigurations', in International conference on field-programmable technology, Proceedings, Taipei, Taiwan, pp. 161 - 168, presented at International conference on field-programmable technology, Taipei, Taiwan, 07 December 2008 - 10 December 2008, http://dx.doi.org/10.1109/FPT.2008.4762379
2008
Malik MA; Diessel OF; Dempster AG, 2007, 'Fast code-phase alignment of GPS signals using Virtex-4 FPGAs', in IGNSS 2007, International Global Navigation Satellite Systems Society 2007, UNSW, Sydney, Australia, presented at International Global Navigation Satellite Systems Society 2007, UNSW, Sydney, Australia, 04 December 2007 - 06 December 2007
2007
Koh S; Diessel OF, 2007, 'Module graph merging and placement to reduce reconfiguration overheads in paged FPGA devices', in International Conference on Field Programmable Logic 2007, Amsterdam, Netherlands, pp. 293 - 298, presented at International Conference on Field Programmable Logic 2007, Amsterdam, Netherlands, 27 August 2007 - 29 August 2007, http://dx.doi.org/10.1109/FPL.2007.4380662
2007
Diessel O; Koh S, 2006, 'Enabling RTR for industry', in Dagstuhl Seminar Proceedings, Schloss Dagstuhl-Leibniz-Zentrum für Informatik, Schloss Dagstuhl-Leibniz-Zentrum für Informatik
2006
Koh LW; Diessel OF, 2006, 'Functional unit chaining: a runtime adaptive architecture for reducing bypass delays', in Advances in computer systems architecture, 11th Asia-Pacific conference, Shanghai, China, pp. 161 - 174, presented at Advances in computer systems architecture, 11th Asia-Pacific conference, Shanghai, China, 06 September 2006 - 08 September 2006
2006
Koh S; Diessel OF, 2006, 'COMMA: a communications methodology for dynamic module-based reconfiguration of FPGAs', in 19th international conference on architecture of computing systems, 19th international conference on architecture of computing systems, Frankfurt, Germany, presented at 19th international conference on architecture of computing systems, Frankfurt, Germany, 13 March 2006 - 17 March 2006
2006
Koh S; Diessel OF, 2006, 'COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs', in IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, New York, NY, United States, pp. 273 - 274, presented at IEEE Symposium on Field-Programmable Custom Computing Machines 2006, Napa Valley, California, USA, 24 April 2006 - 26 April 2006, http://dx.doi.org/10.1109/FCCM.2006.32
2006
Malik U; Diessel OF, 2006, 'The enotropy of FPGA reconfiguration', in 2006 International Conference on Field Programming, International Conference on Field Programming 2006, Madrid, Spain, presented at International Conference on Field Programming 2006, Madrid, Spain, 28 August 2006 - 30 August 2006
2006
Malik U; Diessel O, 2006, 'The entropy of FPGA reconfiguration', in Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, pp. 261 - 266, http://dx.doi.org/10.1109/FPL.2006.311223
2006
Malik U; Diessel O, 2006, 'The entropy of FPGA reconfiguration', in 2006 International Conference on Field Programmable Logic and Applications, IEEE, pp. 1 - 6, IEEE
2006
Koh S; Diessel OF, 2006, 'Communications Infrastructure Generation for Modular FPGA Reconfiguration', in IEEE International Conference in Field Programmable Technology, Bangkok, Thailand, pp. 321 - 324, presented at IEEE International Conference in Field Programmable Technology, Bangkok, Thailand, 13 December 2006 - 15 December 2006, http://dx.doi.org/10.1109/FPT.2006.270338
2006
Malik U; Diessel OF, 2005, 'A configuration memory architecture for fast run-time reconfiguration of FPGAs', in 2005 International conference on field programmable logic (FPL 2005), Finland, pp. 636 - 639, presented at International Conference on Field Programmable Logic 2005, Finland, 24 August 2005 - 26 August 2005, http://dx.doi.org/10.1109/FPL.2005.1515802
2005
Malik U; Diessel OF; della Torre M, 2005, 'A configuration system architecture supporting bit-stream compression for FPGAs', in 10th Asia-Pacific conference on computer systems architecture, Singapore, pp. 415 - 428, presented at 10th Asia-Pacific conference on computer systems architecture, Singapore, 24 October 2005 - 26 October 2005
2005
Malik U; Diessel O, 2004, 'On the placement and granularity of FPGA configurations', in Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on, IEEE, pp. 161 - 168, IEEE
2004
Bergmann N; Diessel O, 2004, 'Message from the general chair and program chair', in Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04
2004
Malik U; Diessel O, 2002, 'An FPGA interpreter with virtual hardware management', in International Parallel Processing Symposium, Springer, pp. 155, Springer, http://dx.doi.org/10.1109/IPDPS.2002.1016553
2002
Guntsch M; Middendorf M; Scheuermann B; Diessel O; ElGindy H; Schmeck H; So K, 2002, 'Population based ant colony optimization on FPGA', in Field-Programmable Technology, 2002.(FPT). Proceedings. 2002 IEEE International Conference on, IEEE, pp. 125 - 132, IEEE, http://dx.doi.org/10.1109/FPT.2002.1188673
2002
Malik U; So K; Diessel O, 2002, 'Resource-aware run-time elaboration of behavioural FPGA specifications', in Field-Programmable Technology, 2002.(FPT). Proceedings. 2002 IEEE International Conference on, IEEE, pp. 68 - 75, IEEE, http://dx.doi.org/10.1109/FPT.2002.1188666
2002
Diessel OF, 2002, 'Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs', in Monien B; Feldmann R (ed.), Euro-Par 2002, Euro-Par 2002, Paderborn Germany, pp. 314 - 317, presented at Euro-Par 2002, Paderborn Germany, 27 August 2002 - 30 August 2002
2002
Brebner G; Diessel O, 2001, 'Chip-based reconfigurable task management', in International Conference on Field Programmable Logic and Applications, Springer, pp. 182 - 191, Springer
2001
Diessel O; Milne G, 2000, 'Compiling process algebraic descriptions into reconfigurable logic', in International Parallel and Distributed Processing Symposium, Springer, pp. 916 - 923, Springer
2000
Diessel O; Milne G, 2000, 'Behavioural language compilation with virtual hardware management', in International Workshop on Field Programmable Logic and Applications, Springer, pp. 707 - 717, Springer
2000
Diessel O, 2000, 'Operating Systems Support for Dynamically Reconfigurable Architectures', in Dagstuhl Seminar Proceedings, Schloss Dagstuhl-Leibniz-Zentrum für Informatik, Schloss Dagstuhl-Leibniz-Zentrum für Informatik
2000
Diessel O; Kearney D; Wigley G, 1999, 'A web-based multiuser operating system for reconfigurable computing', in International Parallel Processing Symposium, Springer, pp. 579 - 587, Springer, http://dx.doi.org/10.1007/BFb0097942
1999
Diessel O; EiGindy H, 1998, 'Partial rearrangements of space-shared FPGAs (Extended abstract)', in Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), pp. 913 - 918, http://dx.doi.org/10.1007/3-540-64359-1_755
1998
Diessel O; ElGindy HA, 1998, 'Partial FPGA rearrangement by local repacking', in FPGA, pp. 259 - 259
1998
Diessel O; ElGindy H, 1998, 'Partial rearrangements of space-shared FPGAs', in International Parallel Processing Symposium, Springer, pp. 913 - 918, Springer
1998
Diessel O; ElGindy H, 1998, 'On scheduling dynamic FPGA reconfigurations', in Australian Conference on Parallel and Real-Time Systems, Springer, pp. 191 - 200, Springer
1998
Diessel O; ElGindy H, 1997, 'Run-time compaction of FPGA designs', in International Workshop on Field Programmable Logic and Applications, Springer, pp. 131 - 140, Springer, http://dx.doi.org/10.1007/3-540-63465-7_218
1997
Diessel O; ElGindy H; Wetherall L, 1996, 'Efficient broadcasting procedures for constrained reconfigurable meshes', in Australasian Conference on Parallel and Real–Time Systems, Citeseer, pp. 85 - 88
1996
Diessel O; ElGindy H; Beresford-Smith B, 1996, 'Partial task compaction reduces queuing delays in partitionable-array machines', in Australasian Conference on Parallel and Real–Time Systems, Citeseer, pp. 186 - 194, Citeseer
1996
Beresford-Smith B; Diessel O; ElGindy H, 1995, 'Optimal algorithms for constrained reconfigurable meshes', in Australian Computer Science Conference, UNIVERSITY OF CANTERBURY, pp. 32 - 41
1995
Beresford-Smith B; Diessel O; ElGindy H, 1994, 'Optimal algorithms for constrained reconfigurable meshes (Extended abstract)', in Australian Transputer and Occam User Group Conference, pp. 28 - 39
1994
Penfold HB; Diessel OF; Bentink MW, 1990, 'A genetic breeding algorithm which exhibits selforganizing in neural networks', in IASTED Int. Symp. Artificial Intelligence Application and Neural Networks, Anaheim, CA: ACTA, pp. 293 - 296, Anaheim, CA: ACTA
1990
Journal articles
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Kroh A; Diessel O, 2019, 'Efficient fine-grained processor-logic interactions on the cache-coherent zynq platform', ACM Transactions on Reconfigurable Technology and Systems, vol. 11, http://dx.doi.org/10.1145/3277506
2019
Zhao Z; Nguyen NTH; Agiakatsikas D; Lee G; Cetin E; Diessel O, 2018, 'Fine-grained module-based error recovery in FPGA-based TMR systems', ACM Transactions on Reconfigurable Technology and Systems, vol. 11, http://dx.doi.org/10.1145/3173549
2018
Nguyen NTH; Agiakatsikas D; Zhao Z; Wu T; Cetin E; Diessel O; Gong L, 2018, 'Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery', Microprocessors and Microsystems, vol. 60, pp. 86 - 95, http://dx.doi.org/10.1016/j.micpro.2018.04.006
2018
Agiakatsikas D; Cetin E; Diessel O, 2018, 'FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs', IEEE Transactions on Aerospace and Electronic Systems, vol. 54, pp. 2695 - 2712, http://dx.doi.org/10.1109/TAES.2018.2828201
2018
Wang C; Li X; Chen Y; Zhang Y; Diessel O; Zhou X, 2017, 'Service-Oriented Architecture on FPGA-Based MPSoC', IEEE Transactions on Parallel and Distributed Systems, vol. 28, pp. 2993 - 3006, http://dx.doi.org/10.1109/TPDS.2017.2701828
2017
Lee G; Cetin E; Diessel O, 2017, 'Fault recovery time analysis for coarse-grained reconfigurable architectures', ACM Transactions on Embedded Computing Systems, vol. 17, http://dx.doi.org/10.1145/3140944
2017
Leong PHW; Amano H; Anderson J; Bertels K; Cardoso JMP; Diessel O; Gogniat G; Hutton M; Lee J; Luk W; Lysaght P; Platzner M; Prasanna VK; Rissa T; Silvano C; So HKH; Wang Y, 2017, 'The first 25 years of the FPL conference: Significant papers', ACM Transactions on Reconfigurable Technology and Systems, vol. 10, http://dx.doi.org/10.1145/2996468
2017
Gong L; Diessel O, 2014, 'Simulation-based functional verification of dynamically reconfigurable systems', ACM Transactions on Embedded Computing Systems (TECS), vol. 13, pp. 97 - 97
2014
Shannon L; Diessel O; Bergmann NW, 2012, 'Guest editorial: Field-programmable technology', Journal of Signal Processing Systems, vol. 67, pp. 1 - 2, http://dx.doi.org/10.1007/s11265-011-0653-3
2012
Koh S; Diessel OF, 2010, 'Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration', ACM Transactions on Reconfigurable Technology and Systems, vol. 3, pp. 1 - 36, http://dx.doi.org/10.1145/1661438.1661442
2010
Scheuermann B; So KK; Guntsch M; Middendorf M; Diessel OF; Elgindy H; Schmeck H, 2004, 'FPGA Implementation of Population-based Ant Colony Optimization', Applied soft computing : the official journal of the World Federation on Soft Computing (WFSC), vol. 4, pp. 303 - 322, http://dx.doi.org/10.1016/j.asoc.2004.03.008
2004
Diessel O; Malik U; So K, 2002, 'Towards high-level specification, synthesis, and virtualization of programmable logic designs', European Conference on Parallel Processing, vol. 2400, pp. 314 - 317
2002
Diessel OF; Milne G, 2001, 'A hardware compiler realizing concurrent processes in reconfigurable logic', IEE Proceedings-Computers and Digital Techniques, vol. 148, pp. 152 - 162, http://dx.doi.org/10.1049/ip-cdt:20010579
2001
Diessel OF; Elgindy H, 2001, 'On dynamic task scheduling for FPGA-based systems', International Journal of Foundations of Computer Science, vol. 12, pp. 645 - 669, http://dx.doi.org/10.1142/S0129054101000709
2001
Diessel OF; Elgindy H; Middendorf M; Schmeck H; Schmidt B, 2000, 'Dynamic scheduling of tasks on partially reconfigurable FPGAs', IEE Proceedings-Computers and Digital Techniques, vol. 147, pp. 181 - 188, http://dx.doi.org/10.1049/ip-cdt:20000485
2000
Beresford-Smith B; Diessel O; ElGindy H, 1996, 'Optimal algorithms for constrained reconfigurable meshes', Journal of Parallel and Distributed Computing, vol. 39, pp. 74 - 78, http://dx.doi.org/10.1006/jpdc.1996.0155
1996
Book Chapters
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Cetin E; Diessel O; Li T; Ambrose J; Fisk T; Parameswaran S; Dempster A, 2016, 'Overview and Investigation of SEU Detection and Recovery Approaches for FPGA-Based Heterogeneous Systems', in FPGAs and Parallel Architectures for Aerospace Applications Soft Errors and Fault-Tolerant Design, Springer, pp. 33 - 46, http://dx.doi.org/10.1007/978-3-319-14352-1_3
2016
Conference Presentations
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Diessel OF, 2015, 'Application, Design & Test of Dynamically Reconfigurable Field-Programmable Gate Array-based Systems', presented at IET/IEEE/EA Joint Institutions Lecture, Engineers Australia, 13 August 2015 - 13 August 2015
2015
Diessel OF, 2015, 'Detecting and Mitigating Radiation-Induced Errors in SRAM-based Field-Programmable Gate Arrays', presented at 12th IEEE International Conference on Electronic Measurement & Instruments (ICEMI’2015), Qingdao, -
2015
Lingkan G; Diessel OF, 2012, 'Simulation-based Functional Verification of Dynamically Reconfigurable Systems', Vol. 13, presented at 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012, Sydney, Australia, 30 January 2012 - 02 February 2012, http://dx.doi.org/10.1145/2560042
2012
Diessel OF, 2007, 'Moving Run-Time Reconfiguration into the Mainstream', presented at Microelectonics Embedded Systems Workshop, Singapore, -
2007
Diessel OF, 2006, 'Reconfigurable computing', presented at Infocommm Development Authority of Singapore, -
2006
Diessel OF; Engel F; Percival T; Temperley N, 2005, 'Reconfigurable Computing Workshop', presented at Reconfigurable Computing Workshop, National ICT Australia, -
2005
Diessel OF, 2003, 'Towards High-Level Specification & Synthesis of Dynamic Process Logic', presented at Dynamic Straming Architectures Workshop, Caltech, -
2003
Books
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Gong L; Diessel O, 2014, Functional Verification of Dynamically Reconfigurable FPGA-based Systems, Springer, http://dx.doi.org/10.1007/978-3-319-06838-1
2014
ElGindy H; Prasanna VK; Schmeck H; Diessel O, 2000, 7th Reconfigurable Architectures Workshop (RAW2000)
2000
Conference Proceedings (Editor of)
add
Diessel OF; Williams J, (ed.), 2004, 'IEEE Conference on Control Applications', Brisbane, Qld, presented at IEEE Conference on Control Applications, Brisbane, Qld, 06 December 2004 - 08 December 2004
2004