Designing hardware, is, well, hard. State-of-the-art design flows use hardware description languages (HDLs) such as Verilog and VHDL to specify hardware architectures and behaviours. However, the process of writing this HDL code is time-consuming and error-prone. Given the increasing demand for increased complexity, there is thus significant desire to reduce design costs and developer effort during hardware specification. One such avenue for automation is provided via Large Language Models (LLMs). These are a type of artificial intelligence (AI), popularised via models such as ChatGPT and OpenAI's Codex. These models have demonstrated significant abilities for software code-writing tasks, but their application within the hardware domain is more nascent. In this project we will thus explore how such AI models can be applied to the automated authorship of hardware code. In order to ensure that designs are correct, code creation should happen in lock-step with testing and verification tools. Overall, we wish to work towards the overall goal of hardware being automatically and correctly produced from specification documentations.


Computer Science and Engineering

Research Area

AI | Hardware design | Large Language Models | Natural Language Processing | EDA

The research will be carried out at UNSW School of Computer Science and Engineering within the hardware and AI research groups. Access to state of the art AI models are available, as are GPU resources for training models should this be necessary. Work will be undertaken with the guidance of an industry sponsor, Woodpecker Technologies, which are specialists in the hardware verification space. Woodpecker will sponsor 50% of the scholarship.

The expected research outcomes may include:

  1. new frameworks for utilizing existing AI models to generate HDL code
  2. methods for combining AI generation with verification tools
  3. new methods or training data for training and evaluating AI for hardware
  4. publications and intellectual property.
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