A channel COder/DECoder (CODEC) is a critical component in communication systems, playing a pivotal role in ensuring the reliability of data transmission. By encoding the data at the transmitter end and decoding it at the receiver end, a channel CODEC mitigates the adverse effects of noise, interference, and signal distortions during transmission. This process significantly enhances the robustness of the communication link, enabling error detection and correction that allows for accurate data retrieval even in challenging environments. The efficiency of a channel codec directly impacts the overall performance of the communication system, including its power consumption, latency, and error rate performance. Consequently, advancements in channel coding technology are fundamental to the development of high throughput, high reliability communication networks, such as future 6G cellular networks, satellite communications, and IoT systems, where high demand for data throughput and ultra reliability of connectivity are paramount.
This project develops a reconfigurable, low complexity, high throughput low density parity check (LDPC) channel codec for next generation communication systems. LDPC codes, used in the 5G standard, offer excellent error correction capability but typically require high computational resources. Our design addresses these limitations with a multi mode LDPC CODEC IP core that adapts its processing complexity, enabling efficient operation across diverse devices and channel conditions.
This project aims to design and implement a reconfigurable high performance decoder IP core for 5G LDPC codes. The scope includes:
- In depth study of LDPC CODEC principles and architecture.
- Architectural design of the decoder, focusing on throughput, resource efficiency, and scalability.
- Hardware implementation and optimization for power and area on commercial grade FPGA platforms.
- Comprehensive verification and benchmarking, demonstrating real world feasibility for reconfigurable communication systems.
School
Electrical Engineering and Telecommunications
Research Area
Low density parity check (LDPC) codes | Encoding/decoding algorithms | FPGA hardware design
Suitable for recognition of Work Integrated Learning (industrial training)?
No
- Research environment
- Expected outcomes
- Supervisory team
- Reference material/links
The candidate will join the Wireless Communications Research Group within the School of Electrical Engineering and Telecommunications at UNSW, working under the supervision of Prof. Jinhong Yuan, Dr Shane Xie, and their research team. The group maintains a vibrant and collaborative research environment, comprising several PhD candidates and experienced research associates engaged in advanced wireless and signal processing topics. The student will work closely with other HDR and thesis students conducting related research and discussions in the laboratory, enabling regular knowledge exchange and peer support.
- FPGA IP core
- Software verification tool in C/C++
- Report/publication/patent
