Dr Tuo Li

Cetin E; Diessel O; Li T; Ambrose J; Fisk T; Parameswaran S; Dempster A, 2016, 'Overview and Investigation of SEU Detection and Recovery Approaches for FPGA-Based Heterogeneous Systems', in FPGAs and Parallel Architectures for Aerospace Applications Soft Errors and Fault-Tolerant Design, Springer, pp. 33 - 46, http://dx.doi.org/10.1007/978-3-319-14352-1_3

Hussain S; Guo H; Li T; Saadat H; Parameswaran S, 2021, 'COPS: A complete oblivious processing system', Microprocessors and Microsystems, vol. 85, pp. 104295 - 104295, http://dx.doi.org/10.1016/j.micpro.2021.104295

Malekpour A; Ragel R; Tuo LI; Javaid H; Ignjatovic A; Parameswaran S, 2020, 'Hardware Trojan mitigation in pipelined MPSoCs', ACM Transactions on Design Automation of Electronic Systems, vol. 25, http://dx.doi.org/10.1145/3365578

Li T; Shafique M; Ambrose JA; Henkel J; Parameswaran S, 2017, 'Fine-Grained Checkpoint Recovery for Application-Specific Instruction-Set Processors', IEEE Transactions on Computers, vol. 66, pp. 647 - 660, http://dx.doi.org/10.1109/TC.2016.2606378

Li T; Ambrose JA; Ragel R; Parameswaran S, 2016, 'Processor design for soft errors: Challenges and state of the art', ACM Computing Surveys, vol. 49, http://dx.doi.org/10.1145/2996357

Saadat H; Li T; Javaid H; Parameswaran S, 2020, 'A sub-range error characterization based selection methodology for approximate arithmetic units', in Proceedings - 33rd International Conference on VLSI Design, VLSID 2020 - Held concurrently with 19th International Conference on Embedded Systems, pp. 84 - 89, http://dx.doi.org/10.1109/VLSID49098.2020.00032

Li T; Ambrose JA; Parameswaran S, 2016, 'RECORD: Reducing register traffic for checkpointing in embedded processors', in Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, pp. 582 - 587, http://dx.doi.org/10.3850/9783981537079_0191

Ambrose JA; Li T; Murphy D; Gargg S; Higgins N; Parameswaran S, 2015, 'ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA', in Proceedings of the IEEE International Conference on VLSI Design, pp. 29 - 34, http://dx.doi.org/10.1109/VLSID.2015.10

Ambrose JA; Ragel RG; Jayasinghe D; Li T; Parameswaran S, 2015, 'Side channel attacks in embedded systems: A tale of hostilities and deterrence', in Proceedings - International Symposium on Quality Electronic Design, ISQED, pp. 452 - 459, http://dx.doi.org/10.1109/ISQED.2015.7085468

Ambrose JA; Higgins N; Chakravarthy M; Garg S; Li T; Murphy D; Ignjatovic A; Parameswaran S, 2015, 'ARCHER: Communication-based predictive architecture selection for application specific multiprocessor Systems-on-Chip', in Proceedings - IEEE International Symposium on Circuits and Systems, pp. 413 - 416, http://dx.doi.org/10.1109/ISCAS.2015.7168658

Li T; Shafique M; Ambrose JA; Rehman S; Henkel J; Parameswaran S, 2013, 'RASTER: Runtime Adaptive Spatial/Temporal Error Resiliency for Embedded Processors', in Proceedings of the 50th Annual Design Automation Conference, ACM, New York, NY, USA, pp. 62:1 - 62:7, presented at Design Automation Conference, Austin, TX, USA, 02 June 2013 - 06 June 2013, http://dx.doi.org/10.1145/2463209.2488809

Ambrose JA; Cassisi V; Murphy D; Li T; Jayasinghe D; Parameswaran S, 2013, 'Scalable performance monitoring of application specific multiprocessor Systems-on-Chip', in 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings, pp. 315 - 320, http://dx.doi.org/10.1109/ICIInfS.2013.6732002

Li T; Shafique M; Rehman S; Radhakrishnan S; Ragel RG; Ambrose JA; Henkel J; Parameswaran S, 2013, 'CSER: HW/SW Configurable Soft-Error Resiliency for Application Specific Instruction-Set Processors', in Macii E (ed.), DATE '13 Proceedings of the Conference on Design, Automation and Test in Europe, EDA Consortium, San Jose, CA, USA, pp. 707 - 712, presented at Design, Automation and Test in Europe 2013, Grenoble, France, 18 March 2013 - 22 March 2013, http://dl.acm.org/event.cfm?id=RE244&CFID=433443141&CFTOKEN=14133246

Li T; Ragel RG; Parameswaran S, 2012, 'Reli: Hardware/Software Checkpoint and Recovery Scheme for Embedded Processors', in Proceedings -Design, Automation and Test in Europe, DATE, IEEE, Piscataway, NJ, United States, pp. 875 - 880, presented at 15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012, Dresden, Germany, 12 March 2012 - 16 March 2012, http://dx.doi.org/10.1109/DATE.2012.6176621

Li T; Ambrose JA; Parameswaran S, 2012, 'Fine-grained Hardware/Software Methodology for Process Migration in MPSoCs', in Hu A (ed.), International Conference on Computer Aided Design (ICCAD), ACM, New York, USA, pp. 508 - 515, presented at IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, 05 November 2012 - 08 November 2012, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6386717&contentType=Conference+Publications