Single-electron transistors (SETs) enable single-shot electron-spin measurement in qubits, producing picoamperes in current differences between the spin states. A computationally efficient equivalent SET macro-model, if available, is invaluable in gauging the tight trade-offs—noise, power, etc.—while designing a CMOS circuit that reads out the SET current. This project aims at developing a first-order model that captures the most essential SET voltage-current and terminal impedance characteristics in Verilog-A. Motivated candidates can extend the work further, incorporating realistic SET large-signal behavior, potentially as a longer-term project.
School
Electrical Engineering and Telecommunications
Research Area
CMOS circuit design | Quantum computing
Suitable for recognition of Work Integrated Learning (industrial training)?
Yes
- Research environment
- Expected outcomes
- Supervisory team
- Reference material/links
The student will work closely with Dr. Arup K. George in co-designing cryo-CMOS quantum readout circuits using the SET model that they develop, gaining insights into a commercially relevant chip design process using industry-standard toolsets and practices.
- Categorize the literature on SET macro-models and compare various modeling approaches.
- Formulate a modeling methodology after determining the basic set of parameters that needs to be modeled.
- Communicate the modeling rationale to a larger research group via a short report or presentation.
- Develop the SET Verilog-A model and demonstrate its functionality, and finally, by co-simulating with a CMOS readout circuit.
- S. Mahapatra, V. Vaish, C. Wasshuber, K. Banerjee and A. M. Ionescu, “Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design,” in IEEE Transactions on Electron Devices, vol. 51, no. 11, pp. 1772-1782, Nov. 2004 (https://doi.org/10.1109/TED.2004.837369)