Soft-Aided Decoding of Staircase Codes for Next-Generation Storage Systems

Error-correcting codes (ECC) are embedded in every modern storage controller to detect and correct bit errors that occur in memory devices during read and write operations. These errors arise from physical effects such as device ageing, charge leakage, manufacturing variations, and electrical noise. ECC is therefore a critical technology that enables reliable operation of SSDs and other data storage systems.

The rapid growth of artificial intelligence (AI) related applications has led to an unprecedented increase in data storage requirements. Modern data centers are increasingly deploying high-capacity flash storage and SSDs to replace traditional hard disk drives (HDDs), creating demand for more powerful and efficient ECC solutions capable of maintaining data integrity at ever-higher storage densities.

Staircase codes are widely recognized as a promising class of forward error correction (FEC) codes for high-throughput storage and communication systems. Conventional staircase code decoders employ iterative bounded-distance decoding (iBDD), which uses only hard-decision information. While this approach offers low complexity and high speed, it does not exploit the reliability information available from the storage channel, limiting error-correction performance and making the decoder susceptible to mis-corrections and error-floor phenomena.

Recent research has demonstrated that soft-aided decoding techniques can significantly improve staircase code performance by incorporating reliability information while retaining the low-complexity hard-decision decoding framework. These techniques help reduce mis-corrections, overcome difficult error patterns, and improve overall decoding capability with only modest increases in computational complexity.

This project will investigate and implement soft-aided decoding algorithms for staircase codes, from algorithm development to hardware realization. Students will model storage channels and decoding algorithms in software environments, evaluate their error-correction performance, and translate selected designs into FPGA implementations for real-time testing and verification. Performance will be assessed using metrics such as BER, UBER, throughput, latency, and resource utilization. The project offers practical experience in error-control coding, digital system design, FPGA prototyping, hardware verification, and storage-controller architectures widely used in modern datacenter and AI applications.